1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a method for manufacturing a capacitor.
2. Description of the Related Art
Most capacitors that are formed in conjunction with other semiconductor devices have a pair of polysilicon electrodes. However, the polysilicon electrodes have some drawbacks including the formation of a depletion region whose thickness may vary. A variable thickness often leads to a variation of capacitance and a degradation of device performance. In the current state of technology, variation in depletion layer thickness often results in an even greater variation in capacitance because the inter-electrode dielectric layer has become thinner due to miniaturization.
FIGS. 1A through 1C are schematic cross-sectional views showing the progression of manufacturing steps for producing a conventional polysilicon electrode capacitor. Since a transistor is also formed in the peripheral circuit region at the same time, the steps for forming the transistor in the peripheral circuit region are also shown in FIGS. 1A through 1C.
As shown in FIG. 1A, a semiconductor substrate 100 having a memory cell region 100a and a peripheral circuit region 100b is provided. The memory cell region 100a has a field isolation structure 102 already formed in the substrate 100. Using chemical vapor deposition and conventional photolithographic techniques, a bottom polysilicon electrode 104 is formed over the field isolation structure 102. Chemical vapor deposition is conducted again to form a dielectric layer 106 over the bottom polysilicon electrode 104.
As shown in FIG. 1B, a thermal oxidation is carried out to form a gate oxide layer 110 over the substrate 100 in the peripheral circuit region 100b. A chemical vapor deposition is next carried out to form a polysilicon layer (not shown in the figure) over the entire silicon substrate 100. The polysilicon layer is patterned to form a top polysilicon electrode 108a above the bottom polysilicon electrode 104 and a polysilicon gate electrode 108b in the peripheral circuit region 100b.
As shown in FIG. 1C, conventional processing steps needed to complete the manufacture of source/drain terminals 114 and spacers 112 on the sidewalls of the gate electrode in the peripheral circuit region 100b are carried out.
In general, the polysilicon electrodes of a capacitor are doped (for example, using arsenic or phosphorus ions) to increase electrical conductivity. However, when a voltage is applied to the capacitor, electric charges are induced at the junction between the electrode and the inter-electrode dielectric layer. The electric charges near the junction cancel most of the effect of produced by the ionic dopants, thereby creating a depletion region.
The depletion region can be regarded as an extension of the inter-electrode dielectric layer. The presence of the depletion region, therefore, increases the effective dielectric layer of the capacitor. In general, the charge storage capacity of a capacitor is inversely proportional to the thickness of the inter-electrode dielectric layer. In other words, a capacitor having a thin dielectric layer is able to store a greater number of charges. However, the formation of a depletion layer increases the thickness of the dielectric layer, and hence reduces the capacitance of the capacitor. In addition, thickness of the depletion layer varies according to the voltage V applied to the electrodes. This can lead to a variation of the voltage coefficient (1/C(dC/dV)) of a capacitor and hence a de-stabilization of the device. Furthermore, polysilicon has a higher resistivity than other metallic materials. Therefore, polysilicon electrodes often limit the ultimate operating speed and performance of the capacitor.